Delay system for generating control signals in ferroelectric memory devices

Abstract

Ferroelectric memory devices and control circuits therefor are presented, in which memory array control and timing signals are derived according to tap outputs from a group of series connected delay elements. Some or all of the individual delay elements comprise one or more trim inputs and a variable delay circuit that provides an output signal a variable delay time after the delay element input signal, where the variable delay is set according to the trim inputs, allowing the control signals to be adjusted or trimmed to accommodate fabrication process variations.