The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2005
Filed:
Apr. 27, 2004
Chen-lun Hsing Chen, North Olmsted, OH (US);
Stanton Weaver, Jr., Northville, NY (US);
Ivan Eliashevich, Maplewood, NJ (US);
Sebastien Libon, New York, NY (US);
Mehmet Arik, Niskayuna, NY (US);
David Shaddock, Troy, NY (US);
Chen-Lun Hsing Chen, North Olmsted, OH (US);
Stanton Weaver, Jr., Northville, NY (US);
Ivan Eliashevich, Maplewood, NJ (US);
Sebastien Libon, New York, NY (US);
Mehmet Arik, Niskayuna, NY (US);
David Shaddock, Troy, NY (US);
GELcore, LLC, Valley View, OH (US);
Abstract
Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (). A metal is applied to the drilled openings to produce a plurality of via arrays (). The LED dice () are flip-chip bonded onto a frontside () of the sub-mount wafer (). The p-type and n-type contacts of each flip-chip bonded LED () electrically communicate with a solderable backside () of the sub-mount wafer () through a via array (). A thermal conduction path () is provided for thermally conducting heat from the flip-chip bonded LED dice () to the solderable backside () of the sub-mount wafer (). Subsequent to the flip-chip bonding, the sub-mount wafer () is separated to produce the surface mount LED packages.