The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Oct. 24, 2002
Abhijit Chatterjee, Atlanta, GA (US);
Dave Majernik, Mt. Airy, MD (US);
Sasikumar Cherubal, Tucson, AZ (US);
Sudip Chakrabarti, San Jose, CA (US);
Ramakrishna Voorakaranam, Phoenix, AZ (US);
Jacob A. Abraham, Austin, TX (US);
Douglas Goodman, Tucson, AZ (US);
Abhijit Chatterjee, Atlanta, GA (US);
Dave Majernik, Mt. Airy, MD (US);
Sasikumar Cherubal, Tucson, AZ (US);
Sudip Chakrabarti, San Jose, CA (US);
Ramakrishna Voorakaranam, Phoenix, AZ (US);
Jacob A. Abraham, Austin, TX (US);
Douglas Goodman, Tucson, AZ (US);
Ardext Technologies, Inc., Tucson, AZ (US);
Abstract
A method for testing a system on a chip or a system on a package (''SOPC') having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.