The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2005

Filed:

Feb. 05, 2002
Applicants:

Jonathan Michael Allen, Rochester, MN (US);

Steven Paul Jones, Rochester, MN (US);

Daniel Frank Moertl, Rochester, MN (US);

Adalberto Guillermo Yanes, Rochester, MN (US);

Inventors:

Jonathan Michael Allen, Rochester, MN (US);

Steven Paul Jones, Rochester, MN (US);

Daniel Frank Moertl, Rochester, MN (US);

Adalberto Guillermo Yanes, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F001/04 ; G06F001/06 ;
U.S. Cl.
CPC ...
Abstract

Embodiments are provided in which clock generation for a PCI bridge and its N attached secondary buses is carried out by using an external PLL clock generator which generates N+1 first clock signals at a first frequency to the bridge and to N multiplexers. The bridge in turn generates N second clock signals to the N multiplexers. Each of the N clock signals generated by the bridge can be at either a second or third frequency. Each of the N multiplexers passes one of the first clock signal and second clock signal to a secondary bus depending on the speed of the slowest adapter on the secondary bus.


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