The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Jul. 18, 2001
Alexei Piatetsky, Reichertsheim, DE;
Frank W. Ahern, Scottsdale, AZ (US);
Alexei Piatetsky, Reichertsheim, DE;
Frank W. Ahern, Scottsdale, AZ (US);
TAO Logic Systems LLC, Las Vegas, NV (US);
Abstract
A methodology by which a host computer can dynamically rebalance PCI-to-PCI bridges to overcome Operating System/BIOS and Chipset limitations in order to allow multiple level PCI buses. This methodology also allows hot-swappable PCI buses to be added and removed without failure. Additionally this method allows for proper I/O resource allocation where previously alliasing preventing this. The present invention overcomes the limitations of an Operating System, such as Windows 2000 and Windows XP, to allow a PCI bus segment to be added by rebalancing the PCI bus tree and resource requirements as needed in order to fit the new PCI bus segment.