Dada decoding

Abstract

An arrangement for selecting the largest of a plurality of input currents (pma (k−1), pmb (k−1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs () for receiving said input currents; a further input () for receiving said further current; an output () for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T, T) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T, T) connected between the input and the common point; and a mirror transistor (T) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current. The currents through transistors (T, T) are summed and sensed by a diode connected transistor (T) whose gate voltage is stored on a capacitor (C, C) by means of respective switches (S, S). The voltages across the capacitors (C, C) are fed via respective switches (S, S) to the gate electrodes of transistors (T, T) whose drain electrodes feed an output current (pmc (k−)) to outputs () of the arrangement. A plurality of such arrangements are used for producing path metric currents for a Viterbi decoder.