Complementary input dynamic logic

Abstract

A complementary input dynamic logic circuit for evaluating a logic function including an N-channel dynamic circuit, a P-channel dynamic circuit and a pass device. The N-channel dynamic circuit determines a complement of the logic function when a clock signal is high by pulling a first evaluation node low if it evaluates. The P-channel dynamic circuit also determines a complement of the logic function when the clock signal is high by pulling a second evaluation node high if the P-channel dynamic circuit evaluates. The pass device is controlled by the first evaluation node and pulls the second evaluation node low if the N-channel dynamic circuit fails to evaluate. An inverted version of the clock signal may be used to drive the second evaluation node low through the pass device. The N- and P-channel dynamic circuits may be implemented with parallel-coupled devices to achieve high fan-in implementations.