The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Feb. 20, 2004
Applicants:
Praveen K. Samudrala, Tampa, FL (US);
Srinivas Katkoori, Tampa, FL (US);
Jeremy Ramos, Tampa, FL (US);
Inventors:
Praveen K. Samudrala, Tampa, FL (US);
Srinivas Katkoori, Tampa, FL (US);
Jeremy Ramos, Tampa, FL (US);
Assignees:
University of South Florida, Tampa, FL (US);
Honeywell Space Systems, Inc., Clearwater, FL (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/003 ; H03K019/173 ; H03K019/177 ; G06F007/38 ;
U.S. Cl.
CPC ...
Abstract
A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.