The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2005

Filed:

Sep. 08, 2003
Applicants:

Kazuhisa Nakata, Osaka, JP;

Katsuhiro Ootani, Nara, JP;

Yasuyuki Sahara, Kyoto, JP;

Shinsaku Sekido, Kyoto, JP;

Inventors:

Kazuhisa Nakata, Osaka, JP;

Katsuhiro Ootani, Nara, JP;

Yasuyuki Sahara, Kyoto, JP;

Shinsaku Sekido, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L029/76 ; H01L029/94 ; H01L031/062 ; H01L031/113 ; H01L031/119 ;
U.S. Cl.
CPC ...
Abstract

Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.


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