The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Jun. 13, 2003
Vijay K. Reddy, Plano, TX (US);
Gianluca Boselli, Richardson, TX (US);
Ekanayake A. Amerasekera, Plano, TX (US);
Vijay K. Reddy, Plano, TX (US);
Gianluca Boselli, Richardson, TX (US);
Ekanayake A. Amerasekera, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A pMOS transistor () is located in an n-well () and has at least one gate (). Transistor () is connected between power pad Vdd or I/O pad () and ground potential Vss (). Gate () is connected to power pad (). The n-well () is capacitively () coupled to ground (), decoupled from the transistor source () and floating under normal operating conditions. Under an ESD event, the diode formed by the source () and the n-well () is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (), improving with shrinking gate width.