The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Jul. 24, 2003
André Dehon, Pasadena, CA (US);
Charles M. Lieber, Lexington, MA (US);
Patrick D. Lincoln, Woodside, CA (US);
John E. Savage, Providence, RI (US);
André DeHon, Pasadena, CA (US);
Charles M. Lieber, Lexington, MA (US);
Patrick D. Lincoln, Woodside, CA (US);
John E. Savage, Providence, RI (US);
California Institute of Technology, Pasadena, CA (US);
President and Fellows of Harvard College, Cambridge, MA (US);
Brown University, Providence, RI (US);
SRI International, Menlo Park, CA (US);
Abstract
A memory array comprising nanoscale wires is disclosed. The nanoscale wires are addressed by means of controllable regions axially and/or radially distributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires and microscale wires. In a two-dimensional embodiment, memory locations are defined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires located in different vertical layers.