Streamlined lasar-to-l200 post-processing for cass

Abstract

A technique of generation of a job for a digital testing unit for a test station from a circuit simulation unit includes completing fault simulation on electronic circuitry, then executing a first program without a fault dictionary, generating a pin map of the electronic circuitry and appending any pin groups, generating test vectors using the pin groups by the first program, generating additional pin groups to accommodate any orphan pins, converting the pin maps and pattern files to pin maps and pattern files, executing the first program to generate the fault dictionary, inputting a minimum scope level of analysis of the circuitry, generating the fault dictionary in fault dictionary data files according to the minimum scope level, generating a fault retriever file from the first program; and transporting the fault dictionary data files, test vectors, new pin maps, and fault retriever file to a second program for run-time fault analysis on the electronic circuitry testing unit. Wire path files and test vectors are generated. The scoring of a mismatch between predicted test responses and actual tester responses can be done by assigning a partial credit for primary output patterns being detected.