The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2005
Filed:
Apr. 16, 2002
Masafumi Yamazaki, Kawasaki, JP;
Takaaki Suzuki, Kawasaki, JP;
Toshikazu Nakamura, Kawasaki, JP;
Satoshi Eto, Kawasaki, JP;
Toshiya Miyo, Kawasaki, JP;
Ayako Sato, Kawasaki, JP;
Takayuki Yoneda, Kawasaki, JP;
Noriko Kawamura, Kawasaki, JP;
Masafumi Yamazaki, Kawasaki, JP;
Takaaki Suzuki, Kawasaki, JP;
Toshikazu Nakamura, Kawasaki, JP;
Satoshi Eto, Kawasaki, JP;
Toshiya Miyo, Kawasaki, JP;
Ayako Sato, Kawasaki, JP;
Takayuki Yoneda, Kawasaki, JP;
Noriko Kawamura, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.