The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2005
Filed:
Aug. 23, 2001
William J. Huff, La Jolla, CA (US);
Lawrence J. Malone, Carlsbad, CA (US);
William J. Huff, La Jolla, CA (US);
Lawrence J. Malone, Carlsbad, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A frequency shift keyed (FSK) receiver for demodulating an incoming transmitted signal comprising: 1) a phase-locked loop for receiving an oscillator reference signal having a frequency F1 and generating a reference carrier frequency signal having a desired frequency N1(F1), wherein N1 may be a non-integer value, the phase-locked loop comprising: a) a phase detector having a first input for receiving the oscillator reference signal and a second input; and b) a frequency divider circuit for dividing an actual frequency of the reference carrier frequency signal by an adjustable integer value N2 applied to a control input of the frequency divider circuit to generate a feedback signal applied to the second input of the phase detector. The FSK receiver further comprises: 2) a frequency discriminator that receives the incoming transmitted signal and the reference carrier frequency signal and generates a correction signal corresponding to a difference between a center frequency of the incoming transmitted signal and the actual frequency of the reference carrier frequency signal; and 3) a delta-sigma modulator controlled by the correction signal operable to generate a sequence of integers having an average value of N2 over a defined time period, wherein the sequence of integers are applied to the control input of the frequency divider circuit.