The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2005

Filed:

Sep. 12, 2003
Applicants:

Tayung Wong, Fremont, CA (US);

Clement C. Fang, Cupertino, CA (US);

David J. Jeffrey, Santa Cruz, CA (US);

Neil N. Duncan, Pleasanton, CA (US);

Inventors:

Tayung Wong, Fremont, CA (US);

Clement C. Fang, Cupertino, CA (US);

David J. Jeffrey, Santa Cruz, CA (US);

Neil N. Duncan, Pleasanton, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C008/00 ;
U.S. Cl.
CPC ...
Abstract

A memory module for use in a two rank memory module system includes a plurality of memory devices and a control circuit. In one embodiment, the control circuit may be configured to generate a chip select signal that is provided to each of the memory devices. The chip select signal may be dependent upon assertions of a first bank chip select signal and a second bank chip select signal received from a memory controller. The control circuit may be further configured to generate an address signal that is provided to each of the memory devices. The address signal may be asserted dependent upon which of the first bank chip select signal and the second bank chip select signal are asserted.


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