The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2005
Filed:
Dec. 20, 2000
Thomas P. Szumla, Lockport, NY (US);
Thomas P. Szumla, Lockport, NY (US);
Eastman Kodak Company, Rochester, NY (US);
Abstract
In connection with a host processing system () capable of delivering commands and raw image data, an apparatus () for formatting raw image data and selectively delivering enhanced image data to a print processing subsystem (). An image data bus section () comprises an image bus interface () coupled to a host processing system () configured to transmit raw image data, a front end memory () coupled to the image bus interface () to receive the raw image data, a back end memory () for receiving the enhanced image data, and a print processing subsystem () coupled to the back end memory () via a print interface () for transmitting print data based on the enhanced image data. A processor bus section () comprises an image processor () and a processor bus interface () adapted to be coupled to the host processing system () in order to communicate print processing instructions between the print processor () and the computer (). A gateway () couples the print processor () to the front end memory () and the back end memory () whereby the print processor () receives the raw image data from the front end memory (), formats the image data, and transmits the enhanced image data to the back end memory (). The image data signals and the processor instruction signals are separated and transmitted over separate buses and bus interfaces to minimize processor I/O wait states and parasitic capacitance.