The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2005

Filed:

Mar. 17, 2004
Applicants:

Ken Matsuura, Chuo-ku, JP;

Takeshi Uematsu, Chuo-ku, JP;

Hiroshi Kawasaki, Chuo-ku, JP;

Takakazu Imai, Chuo-ku, JP;

Koichiro Miura, Chuo-ku, JP;

Inventors:

Ken Matsuura, Chuo-ku, JP;

Takeshi Uematsu, Chuo-ku, JP;

Hiroshi Kawasaki, Chuo-ku, JP;

Takakazu Imai, Chuo-ku, JP;

Koichiro Miura, Chuo-ku, JP;

Assignee:

TDK Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F001/44 ;
U.S. Cl.
CPC ...
Abstract

An adderoutputs a signal VS indicating a value of (Vr−Vo), and a multiplieroutputs a control signal GS indicating a value of G(Vr−Vo) on the basis of the signal VS. An adderoutputs a signal HS on the basis of the control signal GS and a signal FS outputted from an operation circuit, and a PWM signal generating circuitgenerates a PWM signal KS on the basis of the signal HS and a ramp signal RS outputted from a ramp signal circuit, and outputs this signal KS to a switching power supply. A countercounts an on time of the PWM signal KS and retains a count value at a time of receiving a sample signal SMP. The operation circuithas a high-pass filterand an integrator, performs an operation based on a signal DS indicating the count value outputted from the counter, and outputs the signal FS after the operation.


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