The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2005

Filed:

Dec. 12, 2003
Applicants:

Soon-sung Yoo, Gunpo-si, KR;

Youn-gyoung Chang, Uigwang-si, KR;

Heung-lyul Cho, Suwon-si, KR;

Seung-hee Nam, Daejeon, KR;

Inventors:

Soon-Sung Yoo, Gunpo-si, KR;

Youn-Gyoung Chang, Uigwang-si, KR;

Heung-Lyul Cho, Suwon-si, KR;

Seung-Hee Nam, Daejeon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/00 ; G02F001/13 ;
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a liquid crystal display device includes steps of forming a gate line, a gate pad and a gate electrode on a first substrate through a first mask process, forming a data line, a data pad, a source electrode, a drain electrode and an active layer on the first substrate including the gate line, the gate pad and the gate electrode through a second mask process, forming a pixel electrode and a data pad terminal on the first substrate including the data line, the data pad, the source electrode and the drain electrode through a third mask process, forming a passivation layer on an entire surface of the first substrate including the pixel electrode and the data pad terminal, attaching the first substrate including the passivation layer with a second substrate, wherein a gate pad portion including the gate pad and a data pad portion including the data pad are exposed by the second substrate, providing a liquid crystal material into a gap between the first and second substrates, and removing the passivation layer in the gate and data pad portions exposed by the second substrate.


Find Patent Forward Citations

Loading…