Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output

Abstract

A programmable skew clock signal generator has a frequency generator circuit () consistent with the invention produces an output signal Ffrom a reference signal FA frequency accumulator () is preloaded with a preload value Pand receives one reference signal cycle as a clock signal, receives a constant Kas an input thereto, with the frequency accumulator () having a maximum count Kand producing an overflow output. A phase accumulator () is preloaded with a preload value Pand receives one overflow cycle output from the frequency accumulator () as a clock signal and receives a phase offset constant Cas an input thereto. The phase accumulator () has a maximum count Cand produces a phase accumulator () output. A delay line () is clocked by the reference signal Fand produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit () receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output Fwhose phase shift φrelative to Fis a function of Pand P.