The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2005
Filed:
Nov. 02, 2001
John R. Nickolls, Los Altos, CA (US);
Scott D. Johnson, Mountain View, CA (US);
Mark Williams, San Jose, CA (US);
Ethan Mirsky, Mountain View, CA (US);
Kambdur Kirthiranjan, Milpitas, CA (US);
Amrit Raj Pant, Mountain View, CA (US);
Lawrence J. Madar, Iii, San Francisco, CA (US);
John R. Nickolls, Los Altos, CA (US);
Scott D. Johnson, Mountain View, CA (US);
Mark Williams, San Jose, CA (US);
Ethan Mirsky, Mountain View, CA (US);
Kambdur Kirthiranjan, Milpitas, CA (US);
Amrit Raj Pant, Mountain View, CA (US);
Lawrence J. Madar, III, San Francisco, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.