The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2005

Filed:

Sep. 16, 2003
Applicants:

Robert F. Steimle, Austin, TX (US);

Ramachandran Muralidhar, Austin, TX (US);

Wayne M. Paulson, Chandler, AZ (US);

Rajesh A. Rao, Austin, TX (US);

Bruce E. White, Jr., Round Rock, TX (US);

Erwin J. Prinz, Austin, TX (US);

Inventors:

Robert F. Steimle, Austin, TX (US);

Ramachandran Muralidhar, Austin, TX (US);

Wayne M. Paulson, Chandler, AZ (US);

Rajesh A. Rao, Austin, TX (US);

Bruce E. White, Jr., Round Rock, TX (US);

Erwin J. Prinz, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8238 ;
U.S. Cl.
CPC ...
Abstract

A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.


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