The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2005

Filed:

Feb. 13, 2001
Applicants:

Gregory Bollella, Durham, NC (US);

Peter F. Haggar, Raleigh, NC (US);

James A. Mickelson, Cary, NC (US);

David M. Wendt, Apex, NC (US);

Inventors:

Gregory Bollella, Durham, NC (US);

Peter F. Haggar, Raleigh, NC (US);

James A. Mickelson, Cary, NC (US);

David M. Wendt, Apex, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F009/46 ;
U.S. Cl.
CPC ...
Abstract

The present invention provides a method, system, and computer program product for improving scheduling of tasks in systems that accumulate execution time. An upper bound is computed on the amount of additional time each schedulable task in the system may continue to execute after exceeding its predetermined cost, without adversely affecting overall operation of the system (that is, ensuring that the continued execution will not cause invocations of subsequent tasks to fail to meet their execution deadlines). By allowing tasks to run longer, the potential that the task will successfully end is increased, thereby yielding a more efficient overall system. In the preferred embodiment, the extensions are iteratively computed as a fixed percentage of the cost of each task until reaching an amount of time where the system is no longer feasible. The extension values resulting from the iteration before the cost-extended system becomes infeasible are then used at run-time when a particular task encounters an overrun condition. This technique is advantageous in systems where execution of non-schedulable entities (such as occurrence of hardware interrupts) occurs during execution of one or more of the scheduled tasks.


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