The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2005
Filed:
May. 04, 2004
Wayson J. Lowe, Belmont, CA (US);
Eunice Y. D. Hao, Saratoga, CA (US);
Tony K. Ngai, Saratoga, CA (US);
Peter H. Alfke, Los Altos Hills, CA (US);
Wayson J. Lowe, Belmont, CA (US);
Eunice Y. D. Hao, Saratoga, CA (US);
Tony K. Ngai, Saratoga, CA (US);
Peter H. Alfke, Los Altos Hills, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A buffer memory status detection circuit has a binary logic gate (e.g. an OR gate) coupled to a comparator output signal that is asserted when a sum of a first address pointer of a FIFO memory array plus a first offset equals a second address pointer, and to a reset signal. Binary logic provides a binary output (i.e. '0' or '1') in a first clock domain to two synchronization registers in series that convert the output to a second clock domain. An optional pipeline register improves timing of the output in the second clock domain, and is particularly desirable for use with high-speed clocks.