The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2005

Filed:

Nov. 25, 2002
Applicant:

Hendrikus Johannes Janssen, Nijmegen, NL;

Inventor:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/0175 ;
U.S. Cl.
CPC ...
Abstract

An electronic circuit comprising an output driver (DRV) for supplying a control signal (U), comprising a first power supply terminal (V); a second power supply terminal (V); a signal input terminal (IN) for receiving an input signal (U); a signal output terminal (OUT) for supplying the control signal (U); an output transistor (T) having a control terminal, and having a main current path coupled between the first power supply terminal (V) and the signal output terminal (OUT); and a control circuit (CNTRL) responsive to the input signal (U) which supplies a control signal (U) to the control terminal of the output transistor (T), which control circuit (CNTRL) comprises a buffer (BF) having an output which is coupled to the control terminal of the output transistor (T), and having a first power terminal which is coupled to the first power supply terminal (V). The control circuit also supplies a further control signal (U) to the control terminal of a further output transistor (T) which has a main current path coupled between the signal output terminal (OUT) and the second power supply terminal (V). The input signal (U) controls a switch S. In consequence, an input of the buffer is charged with a current value I by means of current source (J) or discharged with a current value I by means of current source (J) and current source (J). Thus a digital signal which is responsive to the input signal (U) is available at the input of the buffer (BF). The control circuit (CNTRL) further comprises a control field effect transistor (T) having a gate, a source connected to a second power terminal of the buffer (BF), and a drain connected to the second power supply terminal (V). A zener diode (Z) is connected between the second power supply terminal (V) and the gate of the control field effect transistor (T). A third current source (J) supplies current through the zener diode (Z). The potential at the gate of the control field effect transistor (T) is stabilized with respect to the potential at the first power supply terminal (V). Therefore also the potential (V) at the source of the control field effect transistor (T), and thus at the second power terminal of the buffer (BF), is more or less stabilized with respect to the potential at the first power supply terminal (V). The control field effect transistor (T) receives the current from the second power terminal of the buffer (BF) and transfers it to the second power supply terminal (V).


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