The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2005
Filed:
Mar. 23, 2004
Hugh Mair, Fairview, TX (US);
Luan A. Dang, Richardson, TX (US);
Xiaowei Deng, Plano, TX (US);
George B. Jamison, Murphy, TX (US);
Tam M. Tran, Austin, TX (US);
Shyh-horng Yang, Plano, TX (US);
David B. Scott, Plano, TX (US);
Hugh Mair, Fairview, TX (US);
Luan A. Dang, Richardson, TX (US);
Xiaowei Deng, Plano, TX (US);
George B. Jamison, Murphy, TX (US);
Tam M. Tran, Austin, TX (US);
Shyh-Horng Yang, Plano, TX (US);
David B. Scott, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.