The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2005
Filed:
Jul. 24, 2001
Sei-hyung Ryu, Cary, NC (US);
Anant Agarwal, Chapel Hill, NC (US);
Mrinal Kanti Das, Durham, NC (US);
Lori A. Lipkin, Raleigh, NC (US);
John W. Palmour, Raleigh, NC (US);
Ranbir Singh, Apex, NC (US);
Sei-Hyung Ryu, Cary, NC (US);
Anant Agarwal, Chapel Hill, NC (US);
Mrinal Kanti Das, Durham, NC (US);
Lori A. Lipkin, Raleigh, NC (US);
John W. Palmour, Raleigh, NC (US);
Ranbir Singh, Apex, NC (US);
Cree, Inc., Durham, NC (US);
Abstract
Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.