The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2005
Filed:
Dec. 04, 2003
William Andrew Nevin, Portadown, GB;
Paul Damien Mccann, Jordanstown, GB;
William Andrew Nevin, Portadown, GB;
Paul Damien McCann, Jordanstown, GB;
Analog Devices, Inc., Norwood, MA (US);
Abstract
A semiconductor substrate () comprising an SOI () formed therein. The semiconductor substrate () comprises first and second wafers () which are directly bonded together along a bond interface (). Prior to bonding the wafers (), a portion () of the second wafer () is ion implanted to form a p+ region for facilitating selective etching thereof to form a buried cavity (), in which a buried insulating layer is subsequently formed under a portion () of the first wafer () for forming the SOI (). After bonding of the first and second wafers () a communicating opening () is etched through the first wafer () to the bond interface (), and the selectively etchable portion () is etched through the communicating opening () to form the buried cavity (). The buried cavity () is then filled with deposited oxide to form the buried insulating layer (). An isolation trench () is formed through the first wafer () to the buried insulating layer () around the portion () for isolating the SOI () from the remainder of the first wafer ().