The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2005
Filed:
Jun. 25, 2004
Tae Hyeok Lee, Kyoungki-do, KR;
Cheol Hwan Park, Seoul, KR;
Dong Su Park, Kyoungki-do, KR;
Ho Jin Cho, Kyoungki-do, KR;
Eun a Lee, Seoul, KR;
Tae Hyeok Lee, Kyoungki-do, KR;
Cheol Hwan Park, Seoul, KR;
Dong Su Park, Kyoungki-do, KR;
Ho Jin Cho, Kyoungki-do, KR;
Eun A Lee, Seoul, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrate, thereby forming a trench; c) thermal-oxidizing the resultant substrate to form a sidewall oxide layer on a surface of the trench; d) nitrifying the sidewall oxide layer through the use of NHannealing; e) depositing a liner aluminum nitride layer on an entire surface of the silicon substrate inclusive of the nitrated sidewall oxide layer; f) depositing a buried oxide layer on the liner aluminum nitride layer to fill the trench; g) performing a chemical mechanical polishing process with respect to the buried oxide layer; and h) eliminating the pad nitride layer.