The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
May. 17, 2002
Applicants:
Pranjal Srivastava, Los Gatos, CA (US);
Ajay Naini, San Jose, CA (US);
Atul Dhablania, San Jose, CA (US);
Inventors:
Pranjal Srivastava, Los Gatos, CA (US);
Ajay Naini, San Jose, CA (US);
Atul Dhablania, San Jose, CA (US);
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F017/50 ;
U.S. Cl.
CPC ...
Abstract
Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.