The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2005

Filed:

Sep. 26, 2002
Applicant:

Moinul I. Syed, Austin, TX (US);

Inventor:

Moinul I. Syed, Austin, TX (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F001/12 ; G06F001/06 ; G06F001/04 ;
U.S. Cl.
CPC ...
Abstract

Methods and apparatus are provided for clock domain conversion in digital processing systems. The methods include operating a first circuit in a fast clock domain with a fast clock and operating a second circuit in a slow clock domain with a slow clock. To transfer signals from the fast clock domain to the slow clock domain, a first synchronization signal is asserted during each fast clock cycle in which a slow clock edge occurs. A fast signal is transferred from the fast clock domain to the slow clock domain on a fast clock edge when the first synchronization signal is asserted. To transfer signals from the slow clock domain to the fast clock domain, a second synchronization signal is asserted during each fast clock cycle that immediately follows a slow clock edge. A slow signal is transferred from the slow clock domain to the fast clock domain on a fast clock edge when the second synchronization signal is asserted.


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