The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2005

Filed:

Aug. 28, 2003
Applicants:

Thomas L. Drabenstott, Cary, NC (US);

Gerald G. Pechanek, Cary, NC (US);

Edwin F. Barry, Vilas, NC (US);

Charles W. Kurak, Jr., Durham, NC (US);

Inventors:

Thomas L. Drabenstott, Cary, NC (US);

Gerald G. Pechanek, Cary, NC (US);

Edwin F. Barry, Vilas, NC (US);

Charles W. Kurak, Jr., Durham, NC (US);

Assignee:

PTS Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F015/82 ; G06F009/302 ;
U.S. Cl.
CPC ...
Abstract

General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.


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