The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Jan. 21, 2004
Kenji Ito, Anjo, JP;
Takuya Harada, Kariya, JP;
Hirofumi Isomura, Kariya, JP;
Denso Corporation, Kariya, JP;
Abstract
A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when 'delay time td+allowance time ta' has elapsed from a start signal Sp. The delay time td is shorter than 'the minimum time width of H level of PWM signal SPWM−allowance time ta'. The delay time td is also time from the variation of level of the PWM signal SPWMto actual variation in the passage of current through a power section.