The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Dec. 12, 2003
Surya Veeraraghavan, Austin, TX (US);
Yang Du, Austin, TX (US);
Glenn O. Workman, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for forming a silicon-on-insulator transistor () includes forming an active region () overlying an insulating layer (), wherein a portion of the active region provides an intrinsic body region (). A body tie access region () is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode () is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion () of the body tie access region. The gate electrode is formed having a substantially constant gate length () along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes () are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion () is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.