The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Sep. 03, 2004
Chih-yu Peng, Hsinchu, TW;
Wei-chuan Lin, Taipei, TW;
Chian-chih Hsiao, Taipei Hsien, TW;
Ta-ko Chuang, Taichung, TW;
Chun-hung Chu, Feng Yuan, TW;
Chih-lung Lin, Taichung, TW;
Chin-mao Lin, Chiayi, TW;
Chih-Yu Peng, Hsinchu, TW;
Wei-Chuan Lin, Taipei, TW;
Chian-Chih Hsiao, Taipei Hsien, TW;
Ta-Ko Chuang, Taichung, TW;
Chun-Hung Chu, Feng Yuan, TW;
Chih-Lung Lin, Taichung, TW;
Chin-Mao Lin, Chiayi, TW;
HannStar Display Corporation, , TW;
Abstract
A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.