The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2005
Filed:
Nov. 20, 2002
Matthew M. Joseph, Milpitas, CA (US);
Zuxu Qin, Stanford, CA (US);
Matthew M. Joseph, Milpitas, CA (US);
Zuxu Qin, Stanford, CA (US);
Sun Microsystems Inc., Santa Clara, CA (US);
Abstract
A method and apparatus is provided by which a die designer can efficiently evaluate package routings associated with a die connection bump layout of a die. The die designer is equipped to determine appropriate placement of die connection bumps around a periphery of the die, designate signal and power assignments for die connection bumps, and check routings between die connection bumps and associated package pins. The die designer can efficiently iterate, without recourse to a package designer, through numerous die connection bump placement and assignment configurations to develop a die connection bump layout that is routable within a package. Thus, time required for iteration between the die designer and the package designer to establish a proper placement and assignment of die connection bumps is substantially reduced. Also, as design variables and constraints change during a die design process, the die designer can efficiently re-evaluate a die-to-package interface without recourse to the package designer.