The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2005
Filed:
Aug. 31, 2001
Axel Scherer, Laguna Beach, CA (US);
Theodore Doll, Arnstadt, DE;
Victor Fuenzalida, Santiago, CL;
California Institute of Technology, Pasadena, CA (US);
Abstract
The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described. By using a very dense interconnect spacing, an inter-pore capacitor structure is obtained between the metalized pores and the pore walls utilized as insulators.