The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2005

Filed:

May. 12, 2003
Applicants:

Chad A. Lindhorst, Seattle, WA (US);

Christopher J. Diorio, Shoreline, WA (US);

Troy N. Gilliland, New Castle, WA (US);

Alberto Pesavento, Seattle, WA (US);

Shail Srinivas, Seattle, WA (US);

Yanjun MA, Issaquah, WA (US);

Terry Hass, St. Louis, MO (US);

Kambiz Rahimi, Redmond, WA (US);

Inventors:

Chad A. Lindhorst, Seattle, WA (US);

Christopher J. Diorio, Shoreline, WA (US);

Troy N. Gilliland, New Castle, WA (US);

Alberto Pesavento, Seattle, WA (US);

Shail Srinivas, Seattle, WA (US);

Yanjun Ma, Issaquah, WA (US);

Terry Hass, St. Louis, MO (US);

Kambiz Rahimi, Redmond, WA (US);

Assignee:

Impinj, Inc., Seattle, WA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C016/06 ;
U.S. Cl.
CPC ...
Abstract

A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.


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