The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2005

Filed:

Feb. 13, 2004
Applicants:

Nicholas J. Stone, Cambridge, GB;

Paul A. Cain, Cambridge, GB;

Thomas M. Brown, Cambridge, GB;

Inventors:

Nicholas J. Stone, Cambridge, GB;

Paul A. Cain, Cambridge, GB;

Thomas M. Brown, Cambridge, GB;

Assignee:

Plastic Logic Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01G004/228 ;
U.S. Cl.
CPC ...
Abstract

An electronic device including first, second and third conductor layers respectively arranged as the source, drain and gate electrodes of a field effect transistor, the third conductor layer being capacitively coupled with both the first and second conductor layers but with the second conductor layer to a greater degree than with the first conductor layer, wherein the electronic device is operable as a non-linear capacitor by applying an alternating voltage across the third conductor layer and the first conductor layer whilst leaving the second conductor layer at a floating potential. Also, an electronic device including a first pair of capacitively coupled first and second conductor layers and a second pair of capacitively coupled third and fourth conductor layers, wherein the first and third conductor layers and the second and fourth conductor layers are arranged as the drain and source electrodes of respective field effect transistors together with one or more gate electrodes conductively connected to either of the first and second conductor layers, wherein the electronic device is operable as a non-linear capacitor by applying an alternating voltage across the first and second conductor layers whilst leaving the third and fourth conductor layers at a floating potential.


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