The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2005

Filed:

Apr. 10, 2003
Applicants:

Kinji Saijo, Yamaguchi-ken, JP;

Kazuo Yoshida, Yamaguchi-ken, JP;

Hiroaki Okamoto, Yamaguchi-ken, JP;

Shinji Ohsawa, Yamaguchi-ken, JP;

Inventors:

Kinji Saijo, Yamaguchi-ken, JP;

Kazuo Yoshida, Yamaguchi-ken, JP;

Hiroaki Okamoto, Yamaguchi-ken, JP;

Shinji Ohsawa, Yamaguchi-ken, JP;

Assignee:

Toyo Kohan Co., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/50 ; B21D033/00 ; H01S004/00 ;
U.S. Cl.
CPC ...
Abstract

A clad plate for forming an interposer for a semiconductor device which can be manufactured at low cost and has good characteristics, an interposer for a semiconductor device, and a method of manufacturing them. Copper foil materials () forming conductive layers () and nickel plating () forming etching stopper layers () are formed and pressed to form a clad plate () for forming an interposer for a semiconductor device. Thus, a clad plate () for forming an interposer for a semiconductor device is manufactured. The clad plate () is selectively etched to form a columnar conductor (), and an insulating layer () is formed on the copper foil material forming a wiring layer (). A bump () for connection of a semiconductor chip and the wiring layer () are formed on the opposite side to the side on which the columnar conductor () is formed. Thus, an interposer for a semiconductor device is manufactured.


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