The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2005
Filed:
May. 17, 2001
Rajesh Manapat, San Jose, CA (US);
Kannan Srinivasagam, San Jose, CA (US);
Rajesh Manapat, San Jose, CA (US);
Kannan Srinivasagam, San Jose, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A method and logic for providing an asynchronous interface to a synchronous memory is disclosed. One embodiment of the present invention provides for a memory having a first logical unit which is operable to generate a synchronized clock signal in response to a chip select signal to the memory. The memory comprises synchronous memory arrays. The synchronized clock signal is input to the selected synchronous memory array. This allows an access to the synchronous memory to complete within a timing budget of the asynchronous interface. Furthermore, the memory has a second logical unit which is operable, in response to the chip select signal and a second signal input to the memory, to put an input/output bus coupled to the synchronous memory into a high impedance state by the end of the memory access. The second input signal may be a read enable or a write enable signal.