The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2005
Filed:
Sep. 04, 2002
Applicants:
Jay Kishora Gupta, Sunnyvale, CA (US);
Amitabha Banerjee, San Jose, CA (US);
Somnath Paul, Fremont, CA (US);
Inventors:
Jay Kishora Gupta, Sunnyvale, CA (US);
Amitabha Banerjee, San Jose, CA (US);
Somnath Paul, Fremont, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F013/00 ;
U.S. Cl.
CPC ...
Abstract
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.
Gupta, Jay. (2005). Fifo memory system and method (U.S. Patent No. 6948030). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6948030
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile