The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2005
Filed:
May. 13, 2004
Andrew Marshall, Dallas, TX (US);
Sumanth Katte Gururajarao, Richardson, TX (US);
Andrew Marshall, Dallas, TX (US);
Sumanth Katte Gururajarao, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Ferroelectric latch type memory devices () are provided, comprising an input circuit () with first and second internal nodes (N, N) coupled with first and second ferroelectric capacitors (C, C), a control circuit (), a restore circuit (), and an output circuit (). The input circuit () operates in a first mode to provide the input data state as first and second voltages on the first and second internal nodes (N, N), respectively. In a second mode, the input circuit () allows the internal nodes (N, N) to float, the restore circuit () operates to restore the data state from the ferroelectric capacitors (C, C) to the internal nodes (N, N), and the output circuit () provides a restored data state as an output (OUT).