The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2005

Filed:

Jun. 07, 2002
Applicants:

Mikimasa Suzuki, Toyohashi, JP;

Shoji Miura, Aichi-ken, JP;

Akira Kuroyanagi, Okazaki, JP;

Noriyuki Iwamori, Okazaki, JP;

Takashi Suzuki, Aichi-ken, JP;

Inventors:

Mikimasa Suzuki, Toyohashi, JP;

Shoji Miura, Aichi-ken, JP;

Akira Kuroyanagi, Okazaki, JP;

Noriyuki Iwamori, Okazaki, JP;

Takashi Suzuki, Aichi-ken, JP;

Assignee:

Denso Corporation, Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L029/76 ;
U.S. Cl.
CPC ...
Abstract

In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and nsource regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each nsource region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.


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