The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2005
Filed:
Jul. 31, 2003
Method for forming a memory integrated circuit with bitlines over gates and capacitors over bitlines
Takayuki Niuya, Plano, TX (US);
Takayuki Niuya, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact regionat a surface of a semiconductor substrate. The transistor, with the exception of the contact region, is covered with a first materialand the first material and the contact region are then covered with a layer of a second material. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layerin the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layerover the first conductive layer, and forming a second conductive layerover the dielectric layer.