The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2005
Filed:
Dec. 12, 2002
Dong-woo Shin, Ichon-shi, KR;
Hyung-bok Choi, Ichon-shi, KR;
Dong-Woo Shin, Ichon-shi, KR;
Hyung-Bok Choi, Ichon-shi, KR;
Hynix Semiconductor Inc., Ichon-shi, KR;
Abstract
A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile