The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Jan. 08, 1999
Applicants:
Akira Nanba, Hyogo, JP;
Kenichi Ogura, Kawasaki, JP;
Manabu Ogino, Hyogo, JP;
Inventors:
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D003/24 ;
U.S. Cl.
CPC ...
Abstract
The digital phase locked loop circuit according to the invention includes a GAC circuit () for calculating the average frequency of the phase locked sampling clock signals in selected channels and for feeding back the calculated average to the phase locked loop. The GAC circuit () includes comparators () for comparing the frequency of the sampling clock signals in each channel with an allowable frequency range and for outputting a frequency error signal with respect to any channel in which the frequency of the sampling clock signals is outside the allowable frequency range.