The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2005
Filed:
May. 28, 1999
David L. Reese, Westborough, MA (US);
John S. Yates, Jr., Needham, MA (US);
Paul H. Hohensee, Nashua, NH (US);
Korbin S. Van Dyke, Sunol, CA (US);
T. R. Ramesh, Newark, CA (US);
Shalesh Thusoo, Milpitas, CA (US);
Gurjeet Singh Saund, Mountain View, CA (US);
Niteen Aravind Patkar, Sunnyvale, CA (US);
David L. Reese, Westborough, MA (US);
John S. Yates, Jr., Needham, MA (US);
Paul H. Hohensee, Nashua, NH (US);
Korbin S. Van Dyke, Sunol, CA (US);
T. R. Ramesh, Newark, CA (US);
Shalesh Thusoo, Milpitas, CA (US);
Gurjeet Singh Saund, Mountain View, CA (US);
Niteen Aravind Patkar, Sunnyvale, CA (US);
ATI International SRL, Hastings, BB;
Abstract
A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.