The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2005

Filed:

Jan. 15, 2003
Applicant:

Yuji Sekido, Kasugai, JP;

Inventor:

Yuji Sekido, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F017/50 ; G06F009/45 ;
U.S. Cl.
CPC ...
Abstract

A design system, a program, a program product and a design method which can easily design a semiconductor integrated circuit element having a decoupling capacitor are provided. In an element region which serves as an IC chip, an input/output blockis arranged, and analog-signal-circuit blocksetc. are arranged. In the capacity insertion regionsetc. of an open regionwhich does not belong to the blocks, unit capacity cellsare arranged in a latticed pattern. Analog wiring linesare arranged between the input/output blockand the analog-signal-circuit blocksetc., and the unit capacity cellsof the capacity insertion regionare respectively connected wiring linesandof power source and GND potentials by via-conductorsand. Thereafter, unit cellsare arranged, and wiring linesfor the connections between the unit cells and between the input/output blockand memory blocksetc. are arranged. Further, the unit capacity cellsof the capacity insertion regionsetc. are respectively connected to power source and GND wiring linesandby via-conductors.


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