The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2005
Filed:
Mar. 24, 2003
Hemant Joshi, Plano, TX (US);
David A. Thomas, Sugar Land, TX (US);
John Bach, Sugar Land, TX (US);
Rand B. Carawan, Stafford, TX (US);
Hemant Joshi, Plano, TX (US);
David A. Thomas, Sugar Land, TX (US);
John Bach, Sugar Land, TX (US);
Rand B. Carawan, Stafford, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of cross-mapping integrated circuit ('IC') elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.