The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2005
Filed:
Apr. 04, 2001
Jiin Lai, Taipei, TW;
Chau-chad Tsai, Taipei, JP;
Sheng-chang Peng, Taipei, TW;
Min-hung Chen, Taipei, TW;
Meng-cheng Ku, Taoyuan, TW;
Huei-li Chou, Taipei, TW;
Jiin Lai, Taipei, TW;
Chau-Chad Tsai, Taipei, JP;
Sheng-Chang Peng, Taipei, TW;
Min-Hung Chen, Taipei, TW;
Meng-Cheng Ku, Taoyuan, TW;
Huei-Li Chou, Taipei, TW;
Via Technologies, Inc., Taipei Hsien, TW;
Abstract
A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of 'write buffer latency' is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.